1. Field of the Invention
The present invention relates to a semiconductor memory device with a redundancy circuit having a fuse and a fuse cutting performance improved.
2. Description of the Related Art
In recent years, an element size becomes small with the high integration of a semiconductor memory device, and it is necessary to consider the relief of element fault. In a technique for the relief of such an element fault, a memory circuit and a redundancy circuit are previously formed and an element of the redundancy circuit is used in place of a fault element of the memory circuit. A fuse is used to switch from the memory circuit to the redundancy circuit.
FIGS. 4A to 4F are cross sectional views showing a method of manufacturing of a conventional semiconductor memory device in order of the process. An internal circuit of the conventional semiconductor memory device contains memory cells and fuses.
First, as shown in FIG. 4A, an element separation oxide film 101, a word line 102 to function as the gate electrode of a memory cell transistor, a diffusion region 103 and a diffusion region 104 are formed on silicon substrate 100 so as to form a MOS transistor Q1. At this time, a large output MOS transistor Q2 is also formed in alperipheral circuit (not shown). Moreover, a bit line 106 is formed of a film of tungsten silicide (WSi) on a lower interlayer insulating film 105 in such a manner that the bit line is connected with the diffusion region 103 of the MOS transistor Q1 of the memory cell by a contact 107. Fuses 108 are formed of a part of the WSi film. An interlayer insulating film is formed on the fuse 108 to cover the fuses 108. An interlayer insulating film 109 is composed of the lower interlayer insulating film 105 and the interlayer insulating film to cover the fuses 108
Next, as shown in FIG. 4B, after forming a accumulation electrode 112 connected with the diffusion region 104 of the memory cell by a contact 111 and a capacitance insulating film 113 are formed, a counter electrode 114 is formed of a polysilicon film. Thus, a capacitor element C is formed. At this time, a part of the polysilicon film is also formed as an etching stopper film 115 in the region for a fuse cutting window to cover the fuses 108.
Next, as shown in FIG. 4C, after a second interlayer insulating film 116 is formed on the polysilicon film 115, the second interlayer insulating film 116 is selectively etched in the region for the fuse cutting window using the polysilicon film 115 as the etching stopper. Thus, an opening 125 is formed on the fuse.
Next, a first metal film is formed for the MOS transistor Q2 of the peripheral circuit 2 (not shown). At this time, the first metal film is formed to cover the opening 125, and is etched back. Thus, a first metal film 120 is formed to cover the inner side wall and peripheral portion of the opening. Subsequently, a portion of the polysilicon film 115 exposed in the bottom of the opening 125 is etched and removed using the first metal film 120 as a mask.
Next, as shown in FIG. 4D, the surface of the first metal film is flattened. That is, after a third interlayer insulating film 121 of a silicon oxide film is formed, an SOG film 122 is formed while a wafer is rotated. Then, project portions of the SOG film 122 are removed by a etching-back method or a CMP (chemical mechanical polishing) method. Thus, the surface of the first metal film is flattened. Moreover, a fourth interlayer insulating film 123 of a silicon oxide film is formed.
Next, as shown in FIG. 4E, a second metal film 126 is formed in the peripheral circuit (not shown). At the same time, a second metal film 127 is formed to have an opening in the opening 125 as shown in FIG. 4E. Then, as shown in FIG. 4F, the fourth interlayer insulating film 123, the SOG film 122, and the third interlayer insulating film 121 are etched in order in the opening 125 such that only the first interlayer insulating film 109 remains directly on the fuses 108 in the opening 125. Thus, the fuse cutting window 131 is formed where only the first interlayer insulating film 109 exists on the fuses 108.
It should be noted that although the subsequent processes are omitted, a cover film and a protection film are formed of insulating films to cover the films such as the SOG film 122 exposed in the fuse cutting window 131.
Therefore, in the fuse cutting window 131 formed in this way, the fuse 108 can be confirmed through the first interlayer insulating film 109 formed in the bottom of the fuse cutting window 131, as shown in FIG. 1. As shown in FIG. 1 by a broken line arrow, if a laser beam LB is selectively irradiated to the fuse 108 through the first interlayer insulating film 109, the fuse 108 is fused and cut by the energy of the laser beam LB. Through cutting of the fuse, the memory cell can be switched from the memory circuit to the redundancy circuit.
By the way, in the highly integrated DRAM in recent years, the memory cells and the fuses are highly integrated. When a plurality of fuses are arranged in parallel as described above, the array pitch is narrowed as small as about 2.5 xcexcm. For this reason, when the fuse is fused and cut using the laser beam LB as described above, the laser beam must be irradiated to the fuse with a high resolution. However, in the conventional method of manufacturing the semiconductor memory device, it is difficult to form the insulating film which exists on the fuse, i.e., the first interlayer insulating film 109 to have a uniform film thickness. For this reason, as shown in FIG. 1, a part of the irradiated laser beam LB is reflected or scattered at the surface of the first interlayer insulating film 109, so that the laser beam LB is irradiated to a fuse 108A in the neighbor of the fuse 108, too. Thus, not only the fuse 108 but also the fuse 108A are fused and cut.
Also, because the film thickness of the first interlayer insulating film 109 remained on the fuse 108 (hereinafter, to be referred to as a remained film thickness) changes depending upon the place, the following problems would occur.
That is, first, the fuse 108 cannot be sometimes cut with a predetermined quantity of irradiation energy of the laser beam LB. For example, if the irradiation energy quantity of the laser beam LB is determined based on the small remained film thickness of the first interlayer insulating film 109, the fuse 108 existing under the first interlayer insulating film 109 having the large remained film thickness cannot be fused and cut.
Second, there would be a case where the surface of the fuse 108 is made rough with the irradiation of predetermined laser beam LB or an element region under the fuse 108 receives any damage. For example, if the irradiation energy of laser beam LB is determined based on the large remained film thickness of the first interlayer insulating film 109, the fuse 108 under the first interlayer insulating film 109 having the small remained film thickness is heated excessively, so that the fuse 108A in the neighbor of the fuse 108 is also fused and cut. Also, the neighborhood of the fuse is burned to weaken the first interlayer insulating film so that moisture becomes easy to invade. Also, the laser beam reaches an element forming region directly below the fuse to give any damage so that leak current increases.
In this way, it is an important problem in the manufacturing process to make the remained film thickness uniform.
The existence of the SOG film could be considered as the reason why the first interlayer insulating film 109 on the fuse 108 cannot be made flat or uniform in thickness. That is, in the manufacturing process shown in FIGS. 4A to 4F, the second interlayer insulating film 116 formed on the polysilicon film 115 is etched to form the opening 125 directly above the fuse 108 using polysilicon film 115 as the etching stopper. Subsequently, the third interlayer insulating film 121, the SOG film 122 and the fourth interlayer insulating film 123 are formed, and then the fourth interlayer insulating film 123, the SOG film 122 and the third interlayer insulating film 121 are etched to form the fuse cutting window 131.
However, when the SOG film 122 is formed, fluid SOG is dropped, and the wafer is rotated to make the SOG film uniform in thickness. For this reason, the centrifugal force due to the wafer rotation is different depending upon the position of the opening 125 and the film thickness of the SOG film 122 cannot be made uniform. According to the inventor""experiment, the remained film thickness of the first interlayer insulating film 109 is in a range of 0.9 to 1.1 xcexcm in the thin portion and in a range of 1.4 to 1.6 xcexcm in the thick portion. Thus, the deviation of about 0.5 xcexcm was observed in the same wafer.
As shown in FIG. 4E, when the etching back is carried out in the SOG film 122, the SOG film 122 remaining above the fuse 108 in the opening 125 is not always in the state that the surface is flat. Therefore, the surface of the fourth interlayer insulating film 123 formed on the SOG film 122 is not in a flat state. For this reason, when the etching back is carried out to these insulating films to form the fuse cutting window 131, a part of the third interlayer insulating film 121 remains on the first interlayer insulating film 109. Thus, the first interlayer insulating film 109 is etched to have the non-uniform thickness. As a result, the surface of the first interlayer insulating film 109 existing on the fuse 108 is not flattened. Also, the SOG film 122 absorbs moisture easily. The SOG film 122 is exposed in the opening 125 in the fuse forming region. Thus, moisture invades from there to make the reliability of the semiconductor memory device decrease.
Therefore, an object of the present invention is to provide a semiconductor memory device and a method of manufacturing the same, in which an insulating film on a fuse is made uniform in thickness in a fuse cutting window so that the fuse can be correctly fused and cut.
In order to achieve an aspect of the present invention, a method of manufacturing a semiconductor memory device, includes:
forming a first interlayer insulating film having at least one fuse in the first interlayer insulating film;
forming an etching stopper film on the first interlayer insulating film;
forming a first layer on the etching stopper film;
etching the first layer to the etching stopper film using a first mask; and
etching the etching stopper film to produce a fuse cutting window.
Here, to form the first layer, a second interlayer insulating film is formed on the etching stopper film, a first metal film is formed to have a first opening which is formed in a region for the fuse cutting window and which has a size larger than the fuse cutting window, and a third interlayer insulating film is formed on the second interlayer insulating film and the first metal film. In this case, to etch the first layer, the third film is etched using the first mask, and then the second interlayer insulating film is etched using the first metal film as a second mask. In this case, the first mask preferably has a size larger than the first opening of the metal film.
Also, in the manufacturing method, the surface of the first interlayer insulating film is flattened before the etching stopper film is formed.
Also, to form a first interlayer insulating film, a fourth interlayer insulating film is formed, a surface of the fourth interlayer insulating film is flattened, at least one fuse is formed on the flattened fourth interlayer insulating film. Then, a fifth interlayer insulating film is formed on the at least one fuse and the flattened fourth interlayer insulating film.
Also, when the etching stopper is conductive, and a second opening is formed through the etching of the second interlayer insulating film, a second metal film is formed on inner side wall of the second opening to connect the etching stopper film to the first metal film, and a sixth interlayer insulating film is formed to cover a bottom of the second opening and the second metal film. In the etching the etching stopper film, the sixth interlayer insulating and then the etching stopper film are etched to produce the fuse cutting window.
Also, it is preferable that the etching stopper film is formed of a material having an etching selection ratio to a material of the second and third interlayer insulating films. The etching stopper film is formed of polysilicon, and is used as one of electrodes of a capacitor of a memory cell. Alternatively, the etching stopper film may be formed of silicon nitride.
In the etching the etching stopper film, the first interlayer insulating film is preferably etched in addition to the etching stopper film such that a film thickness of the etched first interlayer insulating film on the at least one fuse is equal to or less than 1xcexcam. Also, when a plurality of the fuses are formed in the first interlayer insulating film, deviation of the film thicknesses of the etched first interlayer insulating film on the plurality of fuses is preferably equal to or less than 0.3 xcexcm.
In order to achieve another aspect of the present invention, a semiconductor memory device, includes a first interlayer insulating film having at least one fuse therein, an etching stopper film formed on the first interlayer insulating film, a second interlayer insulating film formed on the etching stopper film, a first metal film formed to have a first opening, a third interlayer insulating film formed on the second interlayer insulating film and the first metal film, a fuse cutting window formed to pass through the third interlayer insulating film, the first opening of the first metal film, the second insulating film, and the etching stopper film, a fourth interlayer insulating film formed to cover an inner side wall of the fuse cutting window and the third interlayer insulating film.
Here, the semiconductor memory device may further includes a cell transistor a source and a drain and formed on a semiconductor substrate, and a memory capacitor having two electrodes film to sandwich a capacitance layer and connected to one of the source and the drain of the cell transistor. It is preferable that the etching stopper film is one of the two electrodes.
Also, the semiconductor memory device may further includes a second metal film formed under the fourth interlayer insulating film in the inner side wall of the fuse cutting window to connect the etching stopper film and the first metal film.
Also, the memory capacitor includes a lower one of the two electrodes formed to cover a bottom and inner side wall of a concave section which has formed in the first interlayer insulating film, the capacitance layer formed to cover the first interlayer insulating film and the lower electrode, and an upper one of the two electrodes formed to cover the first interlayer insulating film.
Also, the etching stopper film is preferably formed of polysilicon. Alternatively, the etching stopper film may be formed of silicon nitride.
Also, it is preferable that a distance between a bottom of the fuse cutting window and the at least one fuse is equal to or less than 1 xcexcm. In this case, it is preferable that deviation of the distances between the bottom of the fuse cutting window and the plurality of fuses is equal to or less than 0.3 xcexcm.